The present invention relates to an input-output buffer circuit effecting signal input-output control normally even when a signal having a voltage higher than a power supply voltage of the input-output buffer circuit is inputted from an external source.
As the semiconductor fabrication process uses finer line widths, the power supply voltage for driving a semiconductor integrated circuit (hereafter simply referred to as IC) implemented as a single chip tends to become lower. On the other hand, a commercially available electronic device is constructed in many cases by mounting a plurality of ICs having different specifications on the same printed circuit board. In some cases, therefore, ICs driven with high voltages according to conventional specifications and ICs driven with low voltages according to current and future trends are present on the same electronic device. In this case, an IC is often supplied with an input signal having a voltage higher than a power supply voltage of the IC itself.
In general, an IC has an input-output buffer circuit for effecting the signal input-output control in a stage immediately preceding its output terminal. Signals inputted and outputted via the external terminal pass through the input-output buffer circuit. FIG. 5 is a circuit diagram showing a conventional input-output buffer circuit and its operation.
The IC 100 has an external terminal 17 connected to a signal line 9. In a stage immediately preceding the external terminal 17, the IC 100 has an input-output buffer circuit which includes a PMOS transistor MP and an NMOS transistor MN forming an output driver, an input buffer 16 for inputting a signal fed from the external terminal 17, a NAND gate 31, a NOR gate 32, and an inverter 33.
The PMOS transistor MP is connected at its source to a power supply terminal 12, and connected at its drain to the external terminal 17. The NMOS transistor MN is connected at its source to the ground, and connected at its drain to the external terminal 17.
The NOR gate 32 is supplied at its first input terminal with output data and supplied at its second input terminal with an output enable signal. An output terminal of the NOR gate 32 is connected to the NMOS transistor MN at its gate. The inverter 33 is supplied with the output enable signal and supplies its inverted output to a first input terminal of the NAND gate 31. A second input terminal of the NAND gate 31 is supplied with the output data. An output terminal of the NAND gate 31 is connected to the PMOS transistor MP at its gate.
Operation of the input-output buffer circuit will now be explained. First, in output mode, i.e. when the output enable signal has logic level xe2x80x9cLxe2x80x9d (low), output data of a logic level xe2x80x9cHxe2x80x9d turns on the PMOS transistor MP and turns off the NMOS transistor MN. At this time, therefore, a potential equivalent to a power supply voltage fed from the power supply terminal 12 is supplied to the output terminal 17. A signal of the logic level xe2x80x9cHxe2x80x9d is thus outputted.
On the other hand, output data of a logic level xe2x80x9cLxe2x80x9d turns off the PMOS transistor MP and turns on the NMOS transistor MN. Therefore, the external terminal 17 becomes equal to a ground potential, and a signal of a logic level xe2x80x9cLxe2x80x9d is outputted. In other words, when the output enable signal has a logic level xe2x80x9cLxe2x80x9d, the signal of the logic level indicated by the output data is outputted from the external terminal 17 as it is via mutually connected drains of the PMOS transistor MP and the NMOS transistor MN.
On the other hand, in input mode, i.e. when the output enable signal is provided with a logic level xe2x80x9cHxe2x80x9d (high), both the PMOS transistor MP and the NMOS transistor MN turn off. In other words, the external terminal 17 assumes a high impedance state. Irrespective of the logic state of the output data, the signal outputted to the outside assumes an indefinite state. In this state, a signal inputted from the outside to the external terminal 17 is inputted to an input buffer 16 and processed as input data.
As illustrated, the external terminal 17 of the IC 100 is connected to an external terminal 51 of another IC 200 via the signal line 9. A signal outputted from an input-output buffer circuit 56 included in the IC 200 is inputted to the external terminal 17. The internal circuit of the IC 200 is driven with a voltage higher than the power supply voltage with which the internal circuit of the IC 100 is driven. In FIG. 5, a power supply voltage supplied from a power supply terminal 11 is higher than the power supply voltage from the power supply terminal 12. In some cases, therefore, a signal having a voltage higher than the drive power supply voltage of the IC 100, i.e., a signal having a voltage higher than the voltage fed from the power supply terminal 12 is inputted to the IC 100.
If the drive power supply voltage of the IC 200, i.e., a signal having a voltage supplied from the power supply terminal 11 is inputted to the external terminal 17, then a current flows to the power supply terminal 12 through a parasitic diode 15 of the PMOS transistor MP as illustrated. This current makes the power supply voltage supplied to various circuits in the IC 100 unstable, and causes false operation or destruction of the PMOS transistor MP.
In the conventional input-output buffer circuit, a power supply terminal 13 for supplying a voltage having the same potential as the drive power supply voltage of the IC 200 is provided in the IC 100. The voltage fed from the power supply terminal 13 is applied to the PMOS transistor MP at its back gate. As a result, the external terminal 17 becomes equal in potential to the back gate of the PMOS transistor MP. A current is prevented from flowing to the power supply terminal 12 through the parasitic diode 15.
In the conventional input-output buffer circuit, however, a voltage higher than the voltage applied to other transistors included in the internal circuit is applied to the drains of the PMOS transistor MP and the NMOS transistor MN which form the output driver. Therefore, it is necessary to select a transistor having a high breakdown voltage as each of the PMOS transistor MP and the NMOS transistor MN. Furthermore, with the advance of smaller scale processes, implementation itself of transistors having a high breakdown voltage also becomes difficult.
Furthermore, since the back gate potential of the PMOS transistor MP becomes higher than the potential of the source connected to the power supply terminal 12, the transistor capability of the PMOS transistor MP becomes lower. For achieving a drive capability equivalent to that of ordinary transistors, therefore, it is necessary to increase the transistor size. Furthermore, there is a problem that the IC 100 needs the power supply terminal 13 for supplying the high voltage apart from the power supply terminal 12 for supplying the drive power supply voltage of the internal circuit.
It is an object of the present invention to provide an input-output buffer circuit to which an input signal having a potential higher than the drive power supply voltage can be inputted without using high breakdown voltage transistors.
The above described problems are solved and the object is achieved by the following aspects of the present invention. The input-output buffer circuit according to one aspect of the present invention includes an input buffer; a PMOS transistor and an NMOS transistor for forming an output buffer, drains of the PMOS transistor and the NMOS transistor being connected together; an output switchover circuit for switching an output mode for outputting output data from an external terminal to outside over to an input mode for inputting input data from the external terminal to the input buffer, and vice versa, according to an output enable signal; and a resistor disposed on a current path between the drains of the PMOS transistor and the NMOS transistor and the external terminal, and when a signal having a potential higher than a power supply potential for driving the own input-output buffer circuit is inputted to the external terminal, and thereby a current path extending from the external terminal to a power supply terminal through a parasitic diode of the PMOS transistor is formed, the resistor conducts potential lowering from the potential of the external terminal so as to cause a potential of drains of the PMOS transistor and the NMOS transistor not to exceed a voltage which can be applied to the PMOS transistor and the NMOS transistor and to become a potential which is at least a threshold level of the input buffer.
According to the above-mentioned aspect of the present invention, a resistor is inserted between the drains of the PMOS transistor and the NMOS transistor which form the output driver and the external terminal. Accordingly, even if a signal having a potential higher than the power supply potential for driving the own input-output buffer circuit is inputted to the external terminal, the potential of the signal can be lowered by the potential drop caused by the resistor. It thus becomes possible to always apply a voltage less than a voltage which can be applied to those MOS transistors, to the drains of the PMOS transistor and the NMOS transistor.
Further, it is preferable that the input-output buffer circuit further includes a comparator circuit for comparing the potential of the external terminal with the power supply potential, and the output switchover circuit is supplied with a comparison result from the comparator circuit. When the comparison result indicates that the potential of the external terminal is higher than the power supply potential, the output switchover circuit turns on the NMOS transistor connected at its source to a ground terminal.
Accordingly, the NMOS transistor connected at its source to the ground is turned on when the comparator circuit has judged the potential of the external terminal to be higher than the power supply potential. As a result, a current can be led from the external terminal to the ground terminal through the resistor.
Further, it is preferable that the input-output buffer circuit further includes a comparator circuit for comparing the potential of the external terminal with the power supply potential; and a back gate potential switchover circuit for receiving a comparison result of the comparator circuit. When the comparison result indicates that the potential of the external terminal is higher than the power supply potential, the back gate potential switchover circuit causes a back gate potential of the PMOS transistor to coincide with a ground potential, whereas when the comparison result indicates that the potential of the external terminal is equal to or less than the power supply potential, the back gate potential switchover circuit causes the back gate potential of the PMOS transistor to coincide with the power supply potential.
Accordingly, the back gate potential of the PMOS transistor is made to coincide with the ground potential when the comparator circuit has judged the potential of the external terminal to be higher than the power supply potential. In that case, therefore, a current can be led from the external terminal to the ground terminal through the resistor, the parasitic PNP transistor of the PMOS transistor, and the well resistor of the PMOS transistor.
Further, it is preferable that the input-output buffer circuit further includes a current control circuit responsive to the potential of the external terminal being higher than the power supply potential, for controlling a potential lowered by using the resistor so as to cause the potential lowered by using the resistor to become equal to the power supply potential.
Accordingly, the current control circuit controls the potential of a first end of the resistor so as to cause it to coincide with the power supply potential, when the current control circuit has judged the potential of the first end of the resistor to be higher than the power supply potential. It thus becomes possible to always apply a voltage less than a voltage which can be applied to those MOS transistors, to the drains of the PMOS transistor and the NMOS transistor.